1. Field of the Invention
The present invention relates to a hybrid mounted device and a method of manufacturing the same, and more particularly, to a device structure that corrects the mounting position by utilizing positional deviation amount measuring marks at the time of mounting a chip, and a method of mounting a chip with high accuracy.
2. Description of the Related Art
A hybrid integrated optical device is realized as a small-sized inexpensive optical device. In the device, an active/passive element such as a laser element (LD: laser diode) or a light-sensitive element (PD: photodiode) is flip-chip mounted onto a silicon platform. The silicon platform is a planar optical circuit board in which an optical waveguide is formed. The optical waveguide and the active/passive element are optically coupled by flip-chip mounting.
In mounting technology used in the above optical device, there is known a method of “visual alignment” that can realize high speed and low cost mounting. According to this method, alignment marks are pre-formed on both a silicon platform and a LD/PD chip, and then image of the marks thereon are recognized by a camera. A mounting position of the LD/PD with respect to the platform is subsequently determined based on the positional information of the alignment marks without driving the LD or PD. FIG. 9 and FIG. 10 show a conventional example of an optical device that comprises a silicon platform and an active/passive element mounted thereon by visual alignment.
In the conventional optical device as shown in FIG. 9 and FIG. 10, a semiconductor laser diode (LD) 21 is flip-chip mounted onto a silicon platform 11. An optical waveguide 12 is formed on the silicon platform 11 by a predetermined semiconductor process. The optical waveguide 12 and the semiconductor laser diode 21 are optically coupled. As shown in FIG. 9, four pedestals 14, which fixes the semiconductor laser 21, are formed on the silicon platform 11. An electrode 13, which is electrically coupled to the semiconductor laser 21 directly, is also formed thereon. Furthermore, alignment marks (mounting position marks) are formed on both the semiconductor laser 21 and the silicon platform 11, respectively. In FIG. 9 and FIG. 10, two first alignment marks (first mounting position marks) M11 are formed at the side of the silicon platform 11, and two second alignment marks (second mounting position marks) M12 are formed at the side of the semiconductor laser 21. Both alignment marks M11 and M12 are used for mounting the semiconductor laser 21 onto the silicon platform 11.
As shown in FIG. 9 and FIG. 10, the first alignment marks M11 and the second alignment marks M12 are configured by circular marks for positioning with their radius made different from one another. With this configuration, in mounting the semiconductor laser 21 onto the silicon platform 11, as shown in FIG. 10, a position on the silicon platform 11 to which the semiconductor laser 21 is mounted is determined by positioning the first alignment marks M11 and the second alignment marks M12 such that both the marks M11 and M12 are concentrically superposed with their centers made to accord with each other by employing the visual alignment mounting method.
On the other hand, along with highly-developed performance and function which are required for optical devices in recent years, the requirement for visual alignment with high accuracy in mounting an LD/PD onto a silicon platform is increasing. Especially, in case of the optical device shown in FIG. 9 and FIG. 10 that optically couples the LD and the optical waveguide formed on the silicon platform, the light confinement effect of the optical waveguide has to be enhanced so as to improve the coupling efficiency. In this way, the spot size of the optical waveguide and that of the LD come close to each other, and the ideal maximum coupling efficiency can be improved. However, in this case, since the spot size comes to be small, a slight positional deviation in mounting undesirably brings about a large coupling loss. Accordingly, in order to enhance the light confinement effect of the optical waveguide to improve the coupling efficiency, there is required a chip mounting technology with super high accuracy that can surely make the positional deviation in mounting equal to or less than 2 μm.
In general, in order to realize such high accuracy, there is employed a method of “active alignment” mounting, under which a current is made to flow in an LD through an LD mounting jig to make the LD emit light, and the coupling state with an optical waveguide is monitored by a photodetector to adjust the optical axis. However, employing this method, a particular mounted device is required, and demerits of complicated mounting procedure and elongated mounting time period are significantly large, which makes it difficult to fulfill the cost requirement of the market. Accordingly, so as to improve the mounting accuracy with the cost suppressed low, it is the best way to employ “passive alignment” mounting technology by the visual alignment, which is used in the past, to the utmost extent.
However, in case of the chip mounting by above-described conventional visual alignment, the mounting accuracy is determined depending on mainly the accuracy of image recognition and the accuracy of mechanical driving, and it has been difficult to surely bond an element with a deviation amount equal to or less than 2 μm. In addition, a silicon platform onto which a chip is mounted is manufactured under a semiconductor wafer process employing the stepper exposure or contact exposure. A positional deviation of approximately 1 to 2 μm is brought about by the manufacturing process.
That is, conventionally, there are raised degradation in the mounting accuracy that pertains to the visual alignment and degradation in the mounting accuracy due to the initial positional deviation of alignment marks. Accordingly, even if alignment marks are formed on a layer which is different from that on which an optical waveguide is formed, and the chip mounting accuracy for the alignment marks is mechanically made highly accurate, as shown in FIG. 9 and FIG. 10, since the position of the alignment marks themselves is deviated with respect to the optical waveguide by 1 to 2 μm (refer to the initial positional deviation in the “x” direction shown in FIG. 10), consequently it is difficult to bond a chip certainly with accuracy equal to or less than 2 μm in positional deviation, and a countermeasure for the situation is required.
For example, in case of JP-A-2002-062447, since mounting markers are not concurrently formed at the time of forming an optical waveguide, similar degradation in the mounting accuracy is raised. In addition, since the positional deviation amount and positional deviation direction vary from chip to chip depending on the lot, deflection of wafer, in-plane position on wafer, etc., the initial positional deviation cannot be completely removed.
Furthermore, in the conventional semiconductor wafer process, even if the positional deviation amount between patterns is managed by the vernier caliper pattern as is disclosed in JP-A-H04(1992)-099309, occurrence of the positional deviation of alignment marks in the patterning process, which depends on a device, cannot be prevented essentially. Therefore, only managing the positional deviation amount does not lead to the improvement in the chip mounting accuracy.
Due to above-described plural factors of degradation in the mounting accuracy, in the conventional technique, it has been very difficult to carry out chip mounting certainly with high accuracy equal to or less than 2 μm in positional deviation with desired process yield.